1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device based on transistor memory cells having a charge retention layer, and a method for driving the same.
2. Background Art
In a NAND flash memory having a charge storage layer or a floating electrode as a charge retention layer, with the recent trend of its downscaling, there has been a limit to the number of charges retained in a single memory cell. Decrease in the number of charges retained translates into narrowing of the operable threshold range. This tends to make it difficult to introduce the so-called multilevel techniques.
With a view to avoiding these problems specific to high-density flash memories, U.S. Pat. No. 6,459,622 B1 mentions a nonvolatile memory that uses charge-trapping positions in a memory cell to store additional information. For example, in a NOR flash memory having a charge storage layer, it discloses a technique for storing two bits of information per memory cell by controlling charge-trapping positions in the channel direction. In principle, charge-trapping positions in the direction parallel to the channel and charge-trapping positions in the direction perpendicular to the channel have the possibility of storing additional information. However, the NAND flash memory has no controllability over charge-trapping positions in the channel direction because electrical contact with the source/drain of a memory cell transistor is omitted therein. Furthermore, in a conventional flash memory, there is no means for detecting charge-trapping positions in the direction perpendicular to the channel.
In this context, United States Patent Application Publication No. 2007/0076477 A1 discloses a NOR-type MONOS memory in which the charge storage layer is uniform and the source/drain side is separately programmed.
Furthermore, U.S. Pat. No. 7,202,521 B2 discloses a SONOS memory device, which includes an upper stacked structure forming an upper SONOS memory element in conjunction with a semiconductor layer, and a lower stacked structure provided below the semiconductor layer and forming a lower SONOS memory element in conjunction with the semiconductor layer.